Forum Discussion

SBioo's avatar
SBioo
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Super Long Compilation Time

I've designed a code in OpenCL, targeting Arria 10 FPGAs. In my design, I have specified parameters that control the size of the mode, with respect to the level of parallelism. As I grow this paramet...
DongWang-BJTU's avatar
DongWang-BJTU
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

try to recompile the design with "-dsp-flow=flat", if it does not help, you need to modify the design.

  • SBioo's avatar
    SBioo
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    It seems like -dsp-flow is not part of the "aoc" command options. Is there any specific place that I should include this option?

    • HRZ's avatar
      HRZ
      Icon for Frequent Contributor rankFrequent Contributor
      6 years ago

      The correct switch is "-bsp-flow=flat". However, this switch is only applicable to v17.0+ and you have to manually check the timing report to make sure no signals have failed the timing. Note that using flat compilation disables PCI-E-based reconfiguration and requires configuration through JTAG and depending on your board and environment, you might have to reboot your machine for the kernel to work after that.