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hbens's avatar
hbens
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6 years ago

Streaming data between RTL module and OpenCL kernel using Avalon ST interface

Hi, I'm trying to to use Avalon ST interface to stream data between an OpenCL kernel and RTL module. The avalon ST interface stream data always when ovalid=1 and oready =1 as mentioned in the first...
hbens's avatar
hbens
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6 years ago

Hi,

Thanks for your reply. But iready and ivalid are inputs in my RTL (not outputs), which means I can just read them, I cannot make ireaday as invalid ?

How to set them ? how to manipulate them ? thanks