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hbens's avatar
hbens
Icon for New Contributor rankNew Contributor
5 years ago

Streaming data between RTL module and OpenCL kernel using Avalon ST interface

Hi, I'm trying to to use Avalon ST interface to stream data between an OpenCL kernel and RTL module. The avalon ST interface stream data always when ovalid=1 and oready =1 as mentioned in the first...
AnilErinch_A_Intel's avatar
AnilErinch_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi

Since your source is the OpenCL kernel and RTL is the sink ,

can you make iready as invalid.So that the data streaming can be stopped.

Please let us know the results after trying this.

Thanks and Stay Safe

Anil