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LHinC1's avatar
LHinC1
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6 years ago

Stratix 10 PHY Lite Avalon bus waitrequest issue

Hi everybody , we used Arria 10 FPGA with PHY Lite in our last design. In our new design , we migrate to Stratix 10 and we use PHY Lite to interface DDR4 DRAM. The architecture of Arria 10 PHY Lite i...
LHinC1's avatar
LHinC1
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6 years ago

Hello Aida ,

I downloaded the reference design , and I looked at the code of the reference design.

It involves NIOS II soft core , it differs from what we do , we simply use the PHY Lite in our logic.

Our R&D team have been stuck on this issue for a while ,

could you please help us to contact the PHY Lite code expert to take a look on our PHY Lite connection ?

Thank you so much for your support.

Regards ,

Samson

NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi Samson,

Yes, please send me the code. I will try my best to help you. 😊

Regards,

Aida