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LHinC1's avatar
LHinC1
Icon for New Contributor rankNew Contributor
6 years ago

Stratix 10 PHY Lite Avalon bus waitrequest issue

Hi everybody , we used Arria 10 FPGA with PHY Lite in our last design. In our new design , we migrate to Stratix 10 and we use PHY Lite to interface DDR4 DRAM. The architecture of Arria 10 PHY Lite i...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi Samson,

I have reached out my colleague and I received few inputs as below. Please take a look.

  • Check the register address, we should confirm the lane and pin addresses are correct.
  • Please check the pin assigned correctly.
  • Suspected avl_readdata and avl_writedata are always empty that represents no data receive or send out to Avalon.

Thanks

Regards,

Aida