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LHinC1's avatar
LHinC1
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5 years ago

Stratix 10 PHY Lite Avalon bus waitrequest issue

Hi everybody , we used Arria 10 FPGA with PHY Lite in our last design. In our new design , we migrate to Stratix 10 and we use PHY Lite to interface DDR4 DRAM. The architecture of Arria 10 PHY Lite i...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Samson,

Some additional info:

Regarding the waitrequest stuck, probably it is due to the rd/wr command asserting in wrong way. This might cause the wait request stuck. Please check on this.

Another thing to take note is please try not to send any Avalon transaction before calibration is completed and the controller is ready to accept user Avalon command.

Regards,

Aida

LHinC1's avatar
LHinC1
Icon for New Contributor rankNew Contributor
5 years ago

Hi Aida ,

​

We have carefully checked the wr/rd signals before , anyway we will double check it.

​

We have disconnected the OCT calibration block at the moment , I will check if there is any other calibration in progress.

Thank you so much , the information you provided is very helpful to us.

​

Regards ,

Samson