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BazingaWei's avatar
BazingaWei
Icon for New Contributor rankNew Contributor
6 years ago
Solved

SignalTap influences the designed timing?

i'm using SignalTap by debugging the design, when i compile the design with SignalTap, all timing is correct and the waveform shown by SignalTap GUI is perfect. BUT when i disable the SignalTap in th...
  • KennyT_altera's avatar
    KennyT_altera
    6 years ago

    Thanks for your feedback,


    As mention previously, you have to treat signaltap as any logic inside the fpga. Which means adding a signal tap equivalent to add extra custom logic to your design.


    Sometimes, add additional logic will lead to timing closure and vice versa. If you need help for us to dive into it. You may have to send us a design.qar to look into it.


    Another way to close this type of timing is use DSE. https://www.youtube.com/watch?v=1cc74E3zaeI since you have a design with timing close before.


KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

Since there are no more question, closing the thread. If you have further queries, kindly post a response in the next 15 days.

After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.