Forum Discussion
New ContributorSignalTap influences the designed timing?
Thanks for your feedback,
As mention previously, you have to treat signaltap as any logic inside the fpga. Which means adding a signal tap equivalent to add extra custom logic to your design.
Sometimes, add additional logic will lead to timing closure and vice versa. If you need help for us to dive into it. You may have to send us a design.qar to look into it.
Another way to close this type of timing is use DSE. https://www.youtube.com/watch?v=1cc74E3zaeI since you have a design with timing close before.
Super ContributorYou may refer to here
Basically, you will have to try to control location of the register for TDC implementation.
New ContributorHi, KennyT_intel, thanks for the reply, the reference is helpful, but it is not to my question. I implemented TDC on my device, my question is about Timequest. I show you some figures to make my question clear.
Case 1, compile the whole project without signaltap, i got following report from Timequest Timing Analyzer:
Case 2, compile the whole project with SignalTap, i got following report from Timequest Timing Analyzer:
The two reports differs a lot, my question is why this happens, why there are no 'Warnings' at Worst-Case Timing Paths and What kinds of role does signaltap plays?
Anyway, thanks for reply!
Best Regards
