Intel HLS pipeline::lsu won't dispatch more than 8 request

Some more follow up information I tried increasing the KERNEL_SIDE_MEM_LATENCY to 63 and the number of dispatched request did increase. However, they didn't increase to 64 they increased to 41? Again this is internal to the HLS module as there is no incoming waitrequest signal. This really confuses me as I figured any internal limits would be a factor of 2. Additionally this doesn't seem consistent as someone I am working with reported that they could only get 10 request to dispatch when modifying a slightly different design with a pipelined LSU.

I would really appreciate some help with getting the pipelined LSU to work as using a burst interface increases usage by ~2-4x for most resources and by ~40x for M20K blocks. As the number of channels scales to saturate all the HBM channels this will begin to waste non-negligible amounts of resources impacting our final design performance. Given the Stratix's already limited amount of M20K that waste is really making things difficult.