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fpga_2022
New Contributor
New ContributorRapidio port_initialized
hello,
Recently, I used Rapidio to test the loop test, I checked the clock and reset signal, the port_initialized signal is always low, there is no way to link initialization，quartus prime...
AminT_Intel
Regular Contributor
Regular ContributorHello,
Intel is discontinuing this IP. Please refer to this link: https://www.intel.com/content/www/us/en/products/details/fpga/intellectual-property/interface-protocols/rapid-io-phy.html
Thank you
- AminT_Intel
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
