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zjinf's avatar
zjinf
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

OpenCL to RTL module interface timing?

HI I am not understanding the OpenCL to RTL section on the programming guide. my RTL function simulation is OK with the testbench write by myself , when connect to the openCL, my RTL seems can't ca...
MEIYAN_L_Intel's avatar
MEIYAN_L_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi,

I am looking into it about the generation of signal and known number of clock cycle.

Thanks