openCL memory map

Hi, I am trying to interface a design (gzip) implemented through the OpenCL flow. I went successfully through all the steps, till generating the green bitstream which ran properly on a board equipped with Arria 10. Now I need to interface the design without using the OpenCL layer, so I need to discover where the kernels and the memory sections are mapped: I need to be able to
- program DMAs to transfer data to/from the card,
- give the start to the various kernels,
- exchange scalar parameters with the kernels and
- be informed when some events happen in the FPGA (end of a transfer, stop of a kernel).
As I did not find such information, could you please give me a reference where I could find them?
FYI, I should put the gzip kernel together with another AFU which has been already developed in the OPAE env; also gzip has been developed in the same OPAE env, but we are not able to access it because we cannot find the address map. When I say " developed in the OPAE env", I mean that I took the files generated by openCL for the gzip kernel and I moved them within the project of the other AFU, developed in OPAE env.
I hope that I was able to clarify what I need.