oneAPI on Cyclone10gx

Hi @whitepau_altera I am still running the plain niosv sample simple dma (as it is in the repository without any modification), trying to run in on the hardware and have the cpu (C) interact with the fpga (I confirm the simulation, as detailed in the github repository works).

I added this top node entity:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity test_system is
  port (
    clk : in STD_LOGIC;
    rst : in STD_LOGIC
  );
end entity test_system;

architecture Behavioral of test_system is
    component pd_system is
        port (
            clk_clk                                          : in  std_logic                     := 'X';
            reset_reset                                      : in  std_logic                     := 'X';
            simple_dma_accelerator_device_exception_bus_data : out std_logic_vector(63 downto 0)
        );
    end component pd_system;

    signal pd_system_clk : std_logic;
    signal pd_system_rst : std_logic;

begin
    u0 : pd_system
        port map (
            clk_clk                                          => pd_system_clk,
            reset_reset                                      => pd_system_rst,
            simple_dma_accelerator_device_exception_bus_data => open
        );
    pd_system_clk <= clk;
    pd_system_rst <= rst;

end architecture Behavioral;

I synthesized the project onto my board, I got a few warnings:

1) Critical Warning(12677): No exact pin location assignment(s) for 1 pins of 2 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report

2) No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"

3)Timing requirements not met

clk -6.334 -18110.791 7371 Slow 900mV 100C Model 1
altera_reserved_tck -1.788 -410.899 380 Slow 900mV 100C Model 2

About 1) I think it's referring to the clock/reset signals, I tried to put clock location in the pin planner as you suggested "C10_CLKUSR" but that value it's not accepted, scrolling the dropdown menu I selected "PIN_C10 I/O Bank 2k"; I haven't yet assigned the reset that's why one location is not assigned.

I then used the USB blaster JTAG to program the board (successfully).

then I compiled /kernels/simple_dma/ using "make fpga" rather than "make report" and I got an executable, but when I run it I got this:

tetto@ubuntuoffice:~/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/niosv/kernels/simple_dma/build$ ./simple_dma.fpga
Running on device: SimulatorDevice : Multi-process Simulator (aclmsim0)
terminate called after throwing an instance of 'sycl::_V1::runtime_error'
  what():  Invalid device program image: size is zero -30 (PI_ERROR_INVALID_VALUE)
Aborted (core dumped)
tetto@ubuntuoffice:~/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/niosv/kernels/simple_dma/build$ sudo env "LD_LIBRARY_PATH=$LD_LIBRARY_PATH" ./simple_dma.fpga
terminate called after throwing an instance of 'sycl::_V1::runtime_error'
  what():  No device of requested type available. Please check https://software.intel.com/content/www/us/en/develop/articles/intel-oneapi-dpcpp-system-requirements.html -1 (PI_ERROR_DEVICE_NOT_FOUND)
Aborted

I tried with sudo as I suspected it couldn't find the board; I exported a variable because without it could complain about a missing library, however it screams about a runtime error.

Am I missing something to run this sample on the board and have the C interact with it?

thanks!!