oneAPI on Cyclone10gx

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is there an equivalent platform design, module connection for the vectorial add ("naive implementation")?

No, as I mentioned, the naive solution in that link requires some memory-mapped agent to read the input vectors from and write the output vectors to. You can add an on-chip memory IP to the Platform Designer sample. The IP will have one or more Avalon Agent (slave) interfaces. You need to connect the host (master) interface from your vector_add IP to this agent, and then connect the master interface from the jtag avalon IP to the on-chip memory agent as well; you can use the JTAG interface to fill the on-chip memory with data and then configure the vector_add ip to access it. This is of course a lot of JTAG commands!

An easier solution is the design in the Nios® V softcore processor sample that I shared:
https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/C%2B%2BSYCL_FPGA/ReferenceDesigns/niosv

This uses a soft CPU in place of all the JTAG commands i mentioned, so it fills the on-chip memory with some data and configures and starts the oneAPI IP. In the niosv sample, the oneAPI IP does a simple memory copy rather than a vector add.

The JTAG UART IP in this design is similar to the JTAG Avalon Master IP in the Platform Designer sample. It allows the Nios soft processor to be controlled through a JTAG interface.

of course, you don't have to use on-chip memory; if you want you can use an EMIF IP to connect to the DRAM chips on your Cyclone 10 GX board (but I have no experience using that so someone else will need to help you with that :))