ContributorNo able to run Intel FPGA AI Suite Soc Design Example User Guide example on Intel Arria 10
Hello,
I have an Intel Arria 10 SX SoC FPGA Development Kit and I'm starting with the Intel FPGA AI suite. I was trying to run Intel FPGA AI Suite Soc Design Example User Guide example, but I'm not able.
- If I try to build FPGA bitstream according to 3.3.2 section, I get a license error. I got to another forum thread and it suggests that host pc memory could be full but while this process is running I got 8 or 9 GB over 128GB RAM memory. What could be the problem? You can find attached 'build.log' file
- When I use the precopiled image with the precompiled bitstream, I'm not able to run the resnet-50-tf examples as per section 3.7.1. I compiled the graphs using A10_Performance.arch architecture file according to 3.6.3 section. However, when I run the application on Intel Arria board I an error related to the architecture file.
"Arch check failed:compiledResult arch hash is db8c5e25 cb7fd99d 00000000 00000000 , bitstream arch_hash is d1eb0625 6ebbf77a 00000000 00000000
This check can be disabled by setting environment variable DLA_DISABLE_ARCH_CHECK=1."
It seems that bitstream was not compiled with the same architecture file I compiled the graphs. I tried with others example architecture files available in 'example_architectures' folder with the same result.
In addition setting DLA_DISABLE_ARCH_CHECK=1 I get another error:
"
[ ERROR ] Infer failed
[Step 11/12] Dumping statistics report
count: 4 iterations
system duration: 30022.6073 ms
IP duration: 30442.5643 ms
latency: 30022.4879 ms
system throughput: 0.1332 FPS
number of hardware instances: 1
number of network instances: 1
IP throughput per instance: 0.1314 FPS
IP throughput per fmax per instance: 0.0007 FPS/MHz
IP clock frequency: 200.0000 MHz
estimated IP throughput per instance: 102.3036 FPS (265 MHz assumed)
estimated IP throughput per fmax per instance: 0.3861 FPS/MHz
[Step 12/12] Dumping the output values
[ INFO ] Comparing ground truth file /home/root/resnet-50-tf/sample_images/TF_ground_truth.txt with network Graph_0
top1 accuracy: 0 %
top5 accuracy: 0 %
[ INFO ] Get top results for "Graph_0" graph passed
WaitForDla interrupt timeout with threadId_1
If inference on one batch is expected to take more than 30 seconds, then increase WAIT_FOR_DLA_TIMEOUT in dlia_plugin.cpp and recompile the runtime.
WaitForDla interrupt timeout with threadId_2
If inference on one batch is expected to take more than 30 seconds, then increase WAIT_FOR_DLA_TIMEOUT in dlia_plugin.cpp and recompile the runtime.
WaitForDla interrupt timeout with threadId_3
If inference on one batch is expected to take more than 30 seconds, then increase WAIT_FOR_DLA_TIMEOUT in dlia_plugin.cpp and recompile the runtime."
I'm only following the Intel FPGA AI Suite Soc Design Example User Guide, and I cannot make the example work on my development board. Is it for this board? How I can manage to run the example?
Thank you in advance
