Manual simulation of a HLS design failed

Hello,

I'm replying to my own topic for resolving the issue. The problem was the .do file that is generated when executing NativeLink testbench from Quartus marks the source files generated by HLS Compiler as Verilog 2001 instead of SystemVerilog. Perhaps because the files are with the .v extension instead of .sv, even though they contain SystemVerilog specific code?

Replacing all of the -vlog01compat with -sv option in the .do file (and then running the .do file again in ModelSim) allowed the execution of the test bench.

E.g.:

vlog -sv -work work +incdir+C:/../dsp_hls_streams.prj/quartus {C:/../dsp_hls_streams.prj/quartus/quartus_compile.sv}
vlog -vlog01compat -work dsp_hls +incdir+c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules {c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules/acl_arb_intf.v}
vlog -vlog01compat -work dsp_hls +incdir+c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules {c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules/acl_avm_to_ic.v}

Replace with -sv:

vlog -sv -work work +incdir+C:/../dsp_hls_streams.prj/quartus {C:/../dsp_hls_streams.prj/quartus/quartus_compile.sv}
vlog -sv -work dsp_hls +incdir+c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules {c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules/acl_arb_intf.v}
vlog -sv -work dsp_hls +incdir+c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules {c:/../dsp_hls_streams.prj/quartus/db/ip/dsp_hls/submodules/acl_avm_to_ic.v}