Forum Discussion

sgr's avatar
sgr
Icon for New Contributor rankNew Contributor
3 years ago
Solved

LMI interface in Intel Arria 10 Avalon Streaming Interface for PCI Express

Hi, I have used Intel Arria 10 Avalon Streaming Interface for PCI Express Hard IP as the root port for my design. I was able to get the PCIe Link Up signal (LTSSM state L0 state is high), But w...
  • Wincent_Altera's avatar
    Wincent_Altera
    3 years ago

    Hi,

    We do not receive any response from you to the previous answer that I provided.

    Hence, This thread will be transitioned to community support.

    If you have a new question, feel free to open a new thread to get support from Intel experts.

    Otherwise, the community users will continue to help you on this thread. Thank you

    If you feel your support experience was less than a 9 or 10,

    please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

    Regards,

    Wincent_Intel


Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Yes, to your answer.

Can I know why you need to perform that action ?


Regards,

Wincent_Intel


sgr's avatar
sgr
Icon for New Contributor rankNew Contributor
3 years ago

Hi Wincent_Intel,

Because initially I want to configure my Root port configuration space register with appropriate value and then I want to configure my endpoint register space. So, to configure the Root port configuration space register i need LMI Write interface.