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Shifali15's avatar
Shifali15
Icon for New Contributor rankNew Contributor
4 years ago

L- and H-tile Avalon Streaming Intel FPGA IP for PCI Express as a Root Port

Hi, I want to use L- and H-tile Avalon Streaming Intel FPGA IP for PCI Express as a Root Port. But i not able to understand formation of TLP packets and how to form the TLP header, so please sugges...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

We do not receive any response from you to the previous answer that I provided.

This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or please let me know the cause so that I may improve your future support experience.

Regards,

Wincent_Intel