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Shifali15's avatar
Shifali15
Icon for New Contributor rankNew Contributor
4 years ago

L- and H-tile Avalon Streaming Intel FPGA IP for PCI Express as a Root Port

Hi, I want to use L- and H-tile Avalon Streaming Intel FPGA IP for PCI Express as a Root Port. But i not able to understand formation of TLP packets and how to form the TLP header, so please sugges...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel