Occasional Contributor
Occasional ContributorThx for the reply.
I have two concern about shift register : 1) It seems that shift registers could not be implemented in RAMs, so for large FIFOs, shift regs consumes significant amount of logic resources or sometimes, could not even be generated . 2) shift regs does not have signals to indecate the status of the FIFO (i.e., full or empty), one have to manually implement it by using a couple of counters. However, in opencl counters with complicated controlling circuit includes feedback signals and will degrade the fmax of the design. Is there any other more efficent way to implement the status signals ?
Frequent Contributor1) This is not true. Depending on their size, shift registers are implemented using either a chain of registers or Block RAMs. There is a threshold for the size of the buffer above which the compiler will implement the shift register using Block RAMs. However, the compiler does struggle, and sometimes even crash, when trying to infer really large shift registers (1 MB+).
2) The content of a shift register is supposed to be consumed and shifted once every iteration, and it has no stalling mechanism or full/empty signal. If you need a FIFO with variable consumption rate and stalling mechanism, then a shift register will not work for you. You can still use the standard OpenCL channels within the same kernel to simulate such FIFO, by putting both its read and write points in that kernel, but this would effectively create a cycle and you should be very careful about channel ordering and possibility of deadlocks. You might also be able to use non-blocking channels and increment your counter based on the valid signal of the channel that is exposed in OpenCL, for a [likely] more efficient way of controlling the counter.
