Forum Discussion
JohnShanly
New Contributor
1 year agoPerhaps the RTL library support would do what you want:
ytrezq
New Contributor
1 year agoIn the C analogy using ʀᴛʟ would be equivalent to using a plain .asm file where in .asm you have to care if you use a register or memory which can be handled automatically with a asm/interstic statement. In the ꜰᴘɢᴀ case, this means you still have to clock manually the design.
So this is lower level.
Also, as far I understand, Verilog/ᴠʜᴅʟ code can’t use Sycl code…