Forum Discussion
Occasional ContributorIntel Opencl kernel compiling time
Frequent ContributorAs it seems from the report, you have significant routing congestion in your design which is lengthening the routing process and there is no guarantee routing will ever succeed, either. Make sure you are using the latest BSP and compiler that supports your board and try to simplify your design. Specifically, try to avoid barrel shifters and large register-based buffers. Also, this is the latest version of the Best Practices Guide:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/opencl-sdk/aocl-best-practices-guide.pdf
P.S. Remember that the area estimation is not necessarily accurate and actual utilization could be a lot higher (or lower) than the estimation.
- ADua0
I am using 18.0 Bsp version. I have lot of register , also I have some register structure such as "float __attribute__((register)) sum[4][2][16] ( ", although I am not able to understand how this 3d register is possible , do you know what that means ? could that also be a reason for long compile time
- HRZ
That buffer is not too large but if you have on-chip buffers that are by default implemented using Block RAMs by the compiler due to their size and you force implementation using registers by adding the "__attribute__((register))" attribute, then indeed that could cause routing congestion problems. Having large register-based buffers with a lot of reads/writes will result in high fan-in/fan-out and routing congestion in the area the buffer is implemented.
