Intel Opencl FPGA channels

Question

I have a Opencl design which requires use of Intel opencl Fpga channels for communication between two kernels. I need to know what factors should decide about the channel depth ?

dongwang-bjtu · Answer

The compiler will change the depth during compilation, maybe that why the behavior is not what you have expected.

hrz · Answer

The main factor would be the amount of mismatch in the rate of writing into the channel and reading from it. If these rates are expected to be similar in both of your kernels, then a shallow depth of a few indexes (&lt;20) will suffice and will not use Block RAMs either. If, however, the rate is expected to be very different, then you should keep increasing the depth and measure the performance to see when the performance will become stable.

hrz · Answer

When you have a similar amount of stalling on both the read and the write side, it means the source of stall is not the channel but something else. Indeed increasing channel depth will not help if you only have stalls on the read side but not on the write side.

hrz · Answer

I have no idea. You can check "Section 4.3. Interpreting the Profiling Information" from Best Practices Guide which has extensive information describing how to interpret profiling results and finding sources of bottleneck.

adua0 · Answer

Thanks for the reply. @HRZ​ . Does this also hold for both the cases when stall is at reading and writing side? what I think is having stall at  write side means , channel depth could help but not for reading side ?

Forum Discussion

Intel Opencl FPGA channels

7 Replies

Recent Discussions

Error faced while executing on Agilex FPGA board....

AI Suite System Throughput Issue

Agilex 7 I-Series "aocl diagnose acl0" error following OFS

HLS Compiler 24.1 error - aocl-clang.exe - dll entry point not found

How Do I get the License for HLS?