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ADua0's avatar
ADua0
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Intel Opencl FPGA channels

I have a Opencl design which requires use of Intel opencl Fpga channels for communication between two kernels. I need to know what factors should decide about the channel depth ?
ADua0's avatar
ADua0
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Thanks for the reply. @HRZ​ . Does this also hold for both the cases when stall is at reading and writing side? what I think is having stall at write side means , channel depth could help but not for reading side ?

DongWang-BJTU's avatar
DongWang-BJTU
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

The compiler will change the depth during compilation, maybe that why the behavior is not what you have expected.