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Pan's avatar
Pan
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6 years ago
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Intel HLS (19.3) - Bad implementation of memory.

The expected implementation should have 1 Write (2 shared stores) and 1 Read (1 load) port. But those are the implementations in different cases: REG2_DATA_WIDTH 40 - Wrong implementation. The memo...
  • MEIYAN_L_Intel's avatar
    MEIYAN_L_Intel
    6 years ago

    Hi,

    I had tried to compile the code and the attached code is not able to compile.

    I have added the following line to make it compile:

    #include <HLS/ac_int.h>

    #include <HLS/hls.h>

    #define HLS_COMPONENT component

    #define REG_ADDR WIDTH 64

    This appears to be a regression from 19.1; when compiled using 19.1, the 40-bit and 41-bit both worked nicely. It appears that in the 40-bit case, the compiler decomposes the 40-bit store into power-of-2 stores, 8+8+8+16. A workaround is to set the type in memory to be a 64-bit ac_int.

    Thanks

Pan's avatar
Pan
Icon for New Contributor rankNew Contributor
6 years ago

Hi,

Thanks for your time. I know the behaviour of 19.3 compilation, the fact that 19.1 compiles the right way is interesting. The workaround is obvious, but it will consume resources.

Maybe the question is more about whether this problem will be resolved in the new version of Intel HLS?

Again, thanks for your time and have a great day.