New ContributorIntel HLS (19.3) - Bad implementation of memory.
The expected implementation should have 1 Write (2 shared stores) and 1 Read (1 load) port. But those are the implementations in different cases:
- REG2_DATA_WIDTH 40 - Wrong implementation. The memory ended with multiple writes and ARB. II=33.
- REG2_DATA_WIDTH 41 - Expected implementation. II=1.
- REG2_DATA_WIDTH 48 - Wrong implementation. Multiple stores. II=3
- REG2_DATA_WIDTH 49 - Same as item 1 (40).
- REG2_DATA_WIDTH 64 - Expected implementation. II=1.
There is a method to trick compiler. And that is to define only one write into memory. But this shouldn't be the way to do it. It also raises another problems in more complex components.
The question. Why does this happen and what to do to avoid it? Is it compiler fault I have to circumvent?
The Conclusion. I ended with two possible versions why does this happen:
- The compiler tries to implement optimized memory, therefore it forces multiple narrower stores rather than one wider store.
- The compiler doesn't properly distinguish excluded stores. (Less likely)
Hi,
I had tried to compile the code and the attached code is not able to compile.
I have added the following line to make it compile:
#include <HLS/ac_int.h>
#include <HLS/hls.h>
#define HLS_COMPONENT component
#define REG_ADDR WIDTH 64
This appears to be a regression from 19.1; when compiled using 19.1, the 40-bit and 41-bit both worked nicely. It appears that in the 40-bit case, the compiler decomposes the 40-bit store into power-of-2 stores, 8+8+8+16. A workaround is to set the type in memory to be a 64-bit ac_int.
Thanks
