Forum Discussion
PSriv8
New Contributor
New ContributorIn XILINX there is this DONT_TOUCH or KEEP attribute that will constraint the synthesis tool to not optimize the design and is wondering if there is something similar in Altera that we could use.
I am working on a project related to completion detection in asynchronous circuits and I have chosen the Altera FPGA as my test platform. The decision to use the Altera platform is that it is the mos...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
You can use preserve/keep in the Lite edition. You may find the example of usign preserve in Verilog here:
https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vlog/vlog_file_dir_preserve.htm
VHDL:
https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#hdl/vhdl/vhdl_file_dir_preserve.htm
Thanks.
Best regards,
KhaiY
PSriv8Thank you!! This was really very helpful.
