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BlackByte10xy's avatar
BlackByte10xy
Icon for New Contributor rankNew Contributor
5 years ago

I need to clarify a question about verilog

Hello everybody, I'm studying the primitives in verilog and I don't really see any use for them. I explain: Imagine you want to describe an AND gate, what would you do? a) assign OUT = A & B; ...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

We did not receive any response to the previous question/reply/answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Regards,
Nurina

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