Forum Discussion
BlackByte10xy
New Contributor
New ContributorI need to clarify a question about verilog
Hello everybody,
I'm studying the primitives in verilog and I don't really see any use for them. I explain:
Imagine you want to describe an AND gate, what would you do?
a) assign OUT = A & B;
...
Nurina
Regular Contributor
Regular ContributorHi,
Primitives take up lower memory and can improve simulation performance. Based on my understanding this is because the primitives' behaviour are specified using look-up tables. This method can be helpful because some elements in an FPGA project can be conveniently defined by just using a truth table(combinational) or state table(sequential).
Nurina
