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BlackByte10xy's avatar
BlackByte10xy
Icon for New Contributor rankNew Contributor
4 years ago

I need to clarify a question about verilog

Hello everybody, I'm studying the primitives in verilog and I don't really see any use for them. I explain: Imagine you want to describe an AND gate, what would you do? a) assign OUT = A & B; ...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,


Primitives take up lower memory and can improve simulation performance. Based on my understanding this is because the primitives' behaviour are specified using look-up tables. This method can be helpful because some elements in an FPGA project can be conveniently defined by just using a truth table(combinational) or state table(sequential).


Nurina