I am trying to implement a FIFO using only one single port SRAM in verilog.

I use 2 buffer registers at input side and 2 buffer registers at output side.

Plan is to update SRAM memory every two writes and update the buffer registers at output side every two reads.

I was able to write to SRAM after every two writes but was not able to read it properly. All this depends on control of SRAM Enable and write enable signals.