How to use Avalon-ST to Avalon-MM in msgDMA

Hi,

Avalon-ST (Streaming) interface is used for streaming data, while the Avalon-MM (Memory-Mapped) interface is used for memory-mapped transactions. When you want to transfer data from an Avalon-ST source to a memory location accessible via an Avalon-MM interface, you can use the Modular Scatter-Gather Direct Memory Access (MSGDMA) IP core provided by Altera.

The MSGDMA IP core is designed to handle data transfers between different types of interfaces and supports on-the-fly data movement without CPU intervention. It can be configured to handle transfers from Avalon-ST sources to Avalon-MM sinks.

Here's a high-level overview of how to use MSGDMA for transferring data from Avalon-ST to Avalon-MM:

1. Instantiate the MSGDMA IP Core: You need to instantiate the MSGDMA IP core in your FPGA design. You can configure the MSGDMA IP core using the Intel Quartus Prime software, where you specify the interfaces and other parameters according to your design requirements.
2. Configure the Descriptor Controller: The MSGDMA IP core uses descriptors to define the details of a DMA transfer, such as source address, destination address, transfer length, and control information. You will need to write descriptors to control the data transfer. The descriptors can be written by software running on a CPU or by another hardware component.
3. Write Descriptors: Before the data transfer can begin, you need to write the descriptors that define the transfer. This includes setting up the source address (for Avalon-ST, this might be the base address of the data stream), the destination address (the memory location where the data should be stored), and the amount of data to transfer.
4. Start the Transfer: Once the descriptors are written, you can start the transfer. The MSGDMA IP core will read the descriptors and handle the data transfer according to the specified parameters.
5. Monitor and Manage the Transfer: You can monitor the transfer status through the MSGDMA control and status registers. If necessary, you can also manage the transfer by updating or adding descriptors, pausing, or aborting the transfer.
6. Handle Interrupts: Optionally, you can configure the MSGDMA IP core to generate interrupts upon completion of a transfer or when certain events occur. This allows a CPU or other hardware component to respond to the transfer's progress or completion.

Based on my understanding, while the MSGDMA IP core automates the data transfer process, you still need to write the descriptors that define each transfer's parameters. The IP core does not automatically handle everything without some initial setup and control. The level of automation depends on how you configure and manage the MSGDMA IP core in your system

You may refer for our IP user guide for detail

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pd

Also there is a ready use mSGDMA example design

• https://www.rocketboards.org/foswiki/Projects/Datamover?elq_cid=4474485_ts1717120765750&erpm_id=11957427_ts1717120765750

Let me know if that help you.

Regards,

Wincent_Intel