Forum Discussion

Vicky1's avatar
Vicky1
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi Vinicius,

"Hi,

Please provide your latest working project file(*qar)('Project' Menu->'Archive Project') for replication.

Regards,

Vicky" ---------- I request you again please provide working *qar Archive file for replication as an attachment.

Regards,

Vicky

  • VFerr9's avatar
    VFerr9
    Icon for New Contributor rankNew Contributor
    6 years ago

    No. Nothing wrong. There are already 6 attachments.

    Sexual problem detected.

    Ask your boss: << do you see six attachments? Because Vinicius sees six attachments since December Eleventh. >>

    • Vicky1's avatar
      Vicky1
      Icon for Regular Contributor rankRegular Contributor
      6 years ago

      Hi Vinicius,

      Sexual problem detected. -------- In Intel FPGA community we support only FPGA development & devices related issues so rest of things you need to take care.

      Ask your boss: << do you see six attachments? Because Vinicius sees six attachments since December Eleventh. >> ------- Sure.

      I'm using Altera Quartus 13, 64 bits for web.

      Please, forward it to he who makes quartus next release. ----------- Have you verified with latest Quartus version? please provide specific error/issue.

      https://fpgasoftware.intel.com/18.1/?edition=lite&platform=windows

      People in Intel community are not here to simplify or analyze your projects, they will help you to narrow down your issues if you cooperate them.

      Now I would like to suggest,

      1. Try to compile first your design without error In Quartus latest version & provide screenshot & if you face any error, let us know.
      2. Once it compile successfully then verify it by writing the testbench & tracing waveform.
      3. Then take backup of it & try to simplify with proper HDL syntax & language constraints.
      4. If you need any online training please go through the below link,

      https://www.intel.com/content/www/us/en/programmable/support/training/catalog.html

      Regards,

      Vicky

    • VFerr9's avatar
      VFerr9
      Icon for New Contributor rankNew Contributor
      6 years ago

      Hello, Vicky.

      I did not like discussion about 6 attachments. Your QAR is there. Don't doubt. From zero:

      I studied VHDL with Web release given from my professor.

      I tested at home.

      I went to school. I used FPGL with success.

      Again, I changed at home. Tested with success.

      I could not go to school. (End of semester.) I don't know if that *.sof is what I wanted.

      Simply, I reported everything to the professor and I've sent copy of full story to the people who made the compiler.

      The story is: your compiler compiles sometimes, other times it does not compile deterministically.

      There is an incremental compilation, but...

      Everybody wants a compiler which does the same thing today and tomorrow.

      I know how to solve this with 1 processor. (Java, Delphi, Kylix, C++).

      Without 1 processor, I only know FPGA and the old protoboards.

      The goal was to report those news. If "the company" knows there was a problem with release 13 for Web (free release)

      and if "the company" has as its 2020's priorities to fix it,

      then there is nothing else to discuss.