Occasional Contributor
Contributor@NoahHuguenin here are four additional things you can try to help us narrow down the cause of this issue.
1. does this issue just appear for your design, or is it reproducible with any of the HLS example designs/tutorials?
2. Your question indicates that this design used to work with a different combination of Quartus® Prime/HLS. Can you share those details?
3. This type of error can indicate in incorrectly initialized environment. Please share the output when you initialized i++ using init_hls.bat. On my laptop, it looks like this:
C:\Windows\System32>C:\intelFPGA_pro\24.1\hls\init_hls.bat [i] INFO: Taking this script's directory as the root of the Intel(r) HLS Compiler installation: 'C:\intelFPGA_pro\24.1\hls\' [i] INFO: Quartus is available through your environment: 'C:\intelFPGA_pro\24.1\hls\..\quartus\'-> 'C:\intelFPGA_pro\24.1\quartus\' This setup will make it available on your PATH: 'C:\intelFPGA_pro\24.1\quartus\bin64\quartus_sh.exe' [i] INFO: Platform Designer was installed with Quartus. This setup will make it available on your PATH: 'C:\intelFPGA_pro\24.1\qsys\bin\qsys-script.exe' [i] INFO: ModelSim is available on your PATH: 'C:\intelFPGA_pro\24.1\questa_fse\win64\vsim.exe' [i] INFO: Found Microsoft Visual C++ (MSVC 2017) on your system: 'C:\Program Files (x86)\Microsoft Visual Studio\2017\Professional\Common7\Tools\VsDevCmd.bat' Enabling it as a toolchain for the HLS Compiler... ********************************************************************** ** Visual Studio 2017 Developer Command Prompt v15.9.63 ** Copyright (c) 2017 Microsoft Corporation **********************************************************************
4. A bit of a longshot; but often cryptic compilation errors on Windows are related to issues with long paths. Can you try shortening the paths by giving your component a shorter name and/or compiling it in a shallower file tree?
Occasional ContributorHello, and thank you for your answers!
Based on the information you suggested, I have an update which may explain the previous errors, although it comes with a new problem.
I realized the simulator that was being used was from the Lite 23.1 version which is also installed in this laptop.
It seems to make sense that this would cause an error with missing dependencies, since Agilex 7 libraries would have no reason to be present in a Lite installation.
However, I now have a problem with license files:
a. For Quartus Lite 23.1, Questa FSE (FPGA Starter Edition) was working properly with a node-locked license in the path indicated by the LM_LICENSE_FILE.
b. For Quartus Pro 24.2, I use a floating license in a server. For Questa FE (FPGA Edition), the license is indicated in the MGLS_LICENSE_FILE path, which indicates the server name in the format shown in the following screenshot from the system environment variables.
c. After including the MGLS_LICENSE_FILE path variable, neither FSE or FE detect the license, resulting in this error:
HLS Elaborate verification testbench FAILED.
See c:/intelFPGA_pro/24.2/hls/examples/QRD/test-fpga.prj/debug.log for details.
Error: Missing simulator license for c:\intelFPGA_pro\24.2\questa_fe\win64\vsim.exe. Either:
1) Ensure you have a valid ModelSim license
2) Use the --simulator none flag to skip the verification flow
Based on 4.6.6. Specifying the License for the Questa*-Intel® FPGA Edition..., I set the server license path as MGLS instead of LM.
If I understand 3.1.2.1. ModelSim Software License-Specific Considerations (intel.com) correctly, it is normal that the LM path stopped working, since MGLS path takes precedence. However, I don't see how that would affect the Questa FE floating license.
I tried running the lmutil lmdiag command. According to this, the "intelqsim" license is available at the server and can be checked out. The "intelqsimstarter" also appears in the specified path and it indicates that this is correct node for this license.
So, both licenses are present but none is detected when launching the Questa simulator. Could they be conflicting, or am I missing something?
Before considering that the original post is solved, I would like to test simulating with Questa FPGA Edition to see if this truly solves the library problem.
Thank you in advance,
Noah
