Generated code by Intel HLS does not work

Hi,

I give you an example here,

component int accelerate(int a, int b) {

return a+b ;

}

int main() {

srand (0);

for (int i=0; i<10 ; ++ i) {

int x=rand() % 10 ;

int y=rand() % 10 ;

int z= accelerate (x, y);

printf ("%d + %= ("%d + %= \n", x, y, z);

assert(z == x + y); assert(z == x + y);

}

return 0;

}

accelerate is the component for the FPGA, main() become testbench for component accelerate.

Regarding the testbench top.vhd, is this testbench hand coded by you? The way of the avalon mm to write the testbench have to follow the bfm https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_avalon_verification_ip.pdf.

So, I would strongly recommend you auto create the testbench like the example above, otherwise you will have to learn the bfm.