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HGuer2's avatar
HGuer2
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7 years ago
Solved

Generated code by Intel HLS does not work

I have the following code: hls_always_run_component void Target00(ihc::mm_master<word4_t,ihc::aspace<7>, ihc::awidth<32>, ihc::dwidth<32>, ihc::latency<0>, ihc::waitrequest<true> >& device_5, ihc::...
  • ADent1's avatar
    ADent1
    7 years ago

    Hi,

    The problem was with the avalon_mm_adapter. @HGuer2 will confirm that the message I sent him fixes the issue.

    Sincerely

KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
7 years ago
I try run your design, where do you put your testbench files? Testbench files should be automatic generated if you have a int main function. How do you create your own Testbench files? I would suggest you use the int main function in your .cpp code so that the testbench auto created by not using -simulator none
  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    7 years ago

    By using this, you will get a testbench in Target00.prj/verification. I would recommend you run a design example <quartus_installation_dir>\hls\examples for the HLS to check on this.

    basically, you enable full visibility of all the hdl signal with i++ -ghdl flag

    And run the simulation by

    vsim test00.prj/verification/vsim.wlf

  • HGuer2's avatar
    HGuer2
    Icon for New Contributor rankNew Contributor
    7 years ago

    I cannot use the verification since I am using the hls_always_run_component argument.

    Like I said, you need to create a new ModelSim project where you import all files (generated file by HLS and testbench files { avalon_mm_adapter.vhd, Target00_top.vhd, top.vhd } ).

    The top.vhd is the top-level and contains all the stimulus for the generated HLS IP.

    • HGuer2's avatar
      HGuer2
      Icon for New Contributor rankNew Contributor
      7 years ago

      The detailed procedure above works flawlessly to run the simulation.