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TabetS's avatar
TabetS
Icon for New Contributor rankNew Contributor
2 years ago

FPGA Agelix F-tile

#**Error: (vsim-3043) Unresolved reference to 'eth_f_hw' in eth_f_hw.IP_INST[0.hw_ip_ top.dut.eth_f_0.sip_inst.rx_lane_desired_state.

1 Reply

  • ZiYing_Intel's avatar
    ZiYing_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,


    Thanks for submitting the issue.

    Would you mind to share your .qar file? So that I can try to debug the issue from my side.


    Best regards,

    Zi Ying