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Mickleman's avatar
Mickleman
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Failure to fit an Arria 10 design through insufficent LABs when no problem in reports

Hi

I have a design for a kernel intended for Arria 10. I can compile and successfully run the design with both 1 and 2 copies of the kernel. There are still plenty of resources available so I am now trying to compile 3 copies of the kernel. The reports for this show predicted resource use as follows:

ALUTs: 23%

FFs: 10%

RAMs: 48%

MLABs: 5%

DSPs: 5%

But the compilation fails with the error:

Error (170048): Selected device has 20774 RAM location(s) of type LAB. However, the current design needs more than 20774 to successfully fit. The current design uses 445783 RAM location(s) of type LAB.

I cannot see where the 445,783 LABs comes from looking at the reports. And surely this number would have been around 300,000 in the compilation that was successful.

Could someone point me in the right direction of where to find this excessive LAB use?

Kind regards

Marcus

  • Hi

    With insight from an Intel FPGA expert I have now solved this issue. The problem is that the reports are misreporting the percentage of MLABs that the design is using. The compiler error message is correctly indicating that I am asking for too many MLABs whereas the corresponding Area Analysis report is saying I am using only 65% of them.

    My solution is to check my MLAB use against the known MLAB capacity of the FPGA rather than trust the report.

    Marcus

2 Replies

  • Mickleman's avatar
    Mickleman
    Icon for Occasional Contributor rankOccasional Contributor

    Hi

    With insight from an Intel FPGA expert I have now solved this issue. The problem is that the reports are misreporting the percentage of MLABs that the design is using. The compiler error message is correctly indicating that I am asking for too many MLABs whereas the corresponding Area Analysis report is saying I am using only 65% of them.

    My solution is to check my MLAB use against the known MLAB capacity of the FPGA rather than trust the report.

    Marcus

  • Hi @Mickleman,

    Thank you for posting and sharing the solution in Intel community forum and hope all is well.
    With no further clarification on this thread, it will be transitioned to community support for further help on doubts in this thread.
    Thanks for your questions and as always pleasure having you here.

    Best Wishes
    BB