Eviction policy of burst-coalesced cached non-aligned LSU's cache

The details of the cache are not documented anywhere; however, in my experience:

1- The cache line size is equal to the size of the coalesced memory port. Moreover, by default the cache has 512 or 1024 lines (don't remember exactly since nowadays, I always disable the cache to prevent it from wasting precious Block RAMs).

2- It is probably something extremely simple like FIFO or LIFO. Best case scenario LRU.

3- I am pretty sure the cache doesn't pre-load anything.

In reality, exploiting your application's locality manually will always be more effective and efficient than relying on the extremely simple cache the compiler creates.