Error while linking host code device code in sycl with icpx

Hello,

Lately I have been trying to compile and link a sycl kernel which has the attribute reqd_work_group_size for FPGA hardware with the oneAPI toolkits, specifically the icpx compiler.

Basically, I modified the fast recompile tutorial of oneAPI samples (https://github.com/oneapi-src/oneAPI-samples/tree/main/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile ) to make the sycl structures 2D dimensional and make the kernel to have a nd_range as well as the reqd_work_group_size kernel attribute.

Compiling and linking the kernel into a FPGA image works well, but when i link this image with the host code it crashes showing the next error:

[100%] Generating fast_recompile.fpga
/opt/intel/oneapi/compiler/2024.1/bin/icpx -fintelfpga -qactypes host.o kernel_image.a -o fast_recompile.fpga -I/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/../../../include
libc++abi: terminating due to uncaught exception of type std::bad_alloc: std::bad_alloc
 #0 0x000056039960bd73 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/opt/intel/oneapi/compiler/2024.1/bin/compiler/clang-offload-wrapper+0x3afd73)
 #1 0x000056039960a232 llvm::sys::RunSignalHandlers() (/opt/intel/oneapi/compiler/2024.1/bin/compiler/clang-offload-wrapper+0x3ae232)
 #2 0x000056039960c504 SignalHandler(int) Signals.cpp:0:0
 #3 0x00007fc149201420 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x14420)
 #4 0x00007fc14903e00b raise /build/glibc-LcI20x/glibc-2.31/signal/../sysdeps/unix/sysv/linux/raise.c:51:1
 #5 0x00007fc14901d859 abort /build/glibc-LcI20x/glibc-2.31/stdlib/abort.c:81:7
 #6 0x0000560399715896 (/opt/intel/oneapi/compiler/2024.1/bin/compiler/clang-offload-wrapper+0x4b9896)
 #7 0x00005603996fe5db demangling_terminate_handler() cxa_default_handlers.cpp:0:0
 #8 0x0000560399715553 std::__terminate(void (*)()) cxa_handlers.cpp:0:0
 #9 0x0000560399716f36 (/opt/intel/oneapi/compiler/2024.1/bin/compiler/clang-offload-wrapper+0x4baf36)
#10 0x0000560399716ecf (/opt/intel/oneapi/compiler/2024.1/bin/compiler/clang-offload-wrapper+0x4baecf)
#11 0x0000560399716c28 operator new(unsigned long) (/opt/intel/oneapi/compiler/2024.1/bin/compiler/clang-offload-wrapper+0x4bac28)
#12 0x00005603995e6ca8 llvm::util::PropertyValue::PropertyValue(unsigned char const*, unsigned long) (/opt/intel/oneapi/compiler/2024.1/bin/compiler/clang-offload-wrapper+0x38aca8)
#13 0x00005603994758dd SymPropReader::getPropRegistry() (/opt/intel/oneapi/compiler/2024.1/bin/compiler/clang-offload-wrapper+0x2198dd)
#14 0x000056039946cc22 (anonymous namespace)::BinaryWrapper::createBinDesc(OffloadKind, llvm::SmallVector<std::__1::unique_ptr<(anonymous namespace)::BinaryWrapper::Image, std::__1::default_delete<(anonymous namespace)::BinaryWrapper::Image>>, 4u>&) ClangOffloadWrapper.cpp:0:0
#15 0x00005603994654de main (/opt/intel/oneapi/compiler/2024.1/bin/compiler/clang-offload-wrapper+0x2094de)
#16 0x00007fc14901f083 __libc_start_main /build/glibc-LcI20x/glibc-2.31/csu/../csu/libc-start.c:342:3
#17 0x0000560399461529 _start (/opt/intel/oneapi/compiler/2024.1/bin/compiler/clang-offload-wrapper+0x205529)
icpx: error: unable to execute command: Aborted (core dumped)
icpx: error: clang-offload-wrapper command failed due to signal (use -v to see invocation)
Intel(R) oneAPI DPC++/C++ Compiler 2024.1.0 (2024.1.0.20240308)
Target: x86_64-unknown-linux-gnu
Thread model: posix
InstalledDir: /opt/intel/oneapi/compiler/2024.1/bin/compiler
Configuration file: /opt/intel/oneapi/compiler/2024.1/bin/compiler/../icpx.cfg
icpx: note: diagnostic msg: Error generating preprocessed source(s).

Is there a way to compile this kernel like in the example, separating host and device code?

Thanks

I leave down below the modified code of the fast_recompile files, as well as all the compilation messages printed.

host.cpp code

//==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================

#include <iostream>
#include <vector>

#include <sycl/sycl.hpp>
#include <sycl/ext/intel/fpga_extensions.hpp>

#include "exception_handler.hpp"

// This code sample demonstrates how to split the host and FPGA kernel code into
// separate compilation units so that they can be separately recompiled.
// Consult the README for a detailed discussion.
//  - host.cpp (this file) contains exclusively code that executes on the host.
//  - kernel.cpp contains almost exclusively code that executes on the device.
//  - kernel.hpp contains only the forward declaration of a function containing
//    the device code.
#include "kernel.hpp"

using namespace sycl;

// the tolerance used in floating point comparisons
constexpr float kTol = 0.001;

// the array size of vectors a, b and c
constexpr size_t kArraySize = 64;

int main() {
  std::vector<float> vec_a(kArraySize*kArraySize);
  std::vector<float> vec_b(kArraySize*kArraySize);
  std::vector<float> vec_r(kArraySize*kArraySize);

  // Fill vectors a and b with random float values
  for (size_t i = 0; i < kArraySize; i++) {
    vec_a[i] = rand() / (float)RAND_MAX;
    vec_b[i] = rand() / (float)RAND_MAX;
  }

  // Select either the FPGA emulator, FPGA simulator or FPGA device
#if FPGA_SIMULATOR
  auto selector = sycl::ext::intel::fpga_simulator_selector_v;
#elif FPGA_HARDWARE
  auto selector = sycl::ext::intel::fpga_selector_v;
#else  // #if FPGA_EMULATOR
  auto selector = sycl::ext::intel::fpga_emulator_selector_v;
#endif

  try {

    // Create a queue bound to the chosen device.
    // If the device is unavailable, a SYCL runtime exception is thrown.
    queue q(selector, fpga_tools::exception_handler);

    auto device = q.get_device();

    std::cout << "Running on device: "
              << device.get_info<sycl::info::device::name>().c_str()
              << std::endl;

    // create the device buffers
    buffer device_a(vec_a.data(), range<2>(kArraySize,kArraySize));
    buffer device_b(vec_b.data(), range<2>(kArraySize,kArraySize));
    buffer device_r(vec_r.data(), range<2>(kArraySize,kArraySize));

    // The definition of this function is in a different compilation unit,
    // so host and device code can be separately compiled.
    RunKernel(q, device_a, device_b, device_r, kArraySize, 16);

  } catch (exception const &e) {
    // Catches exceptions in the host code
    std::cerr << "Caught a SYCL host exception:\n" << e.what() << "\n";

    // Most likely the runtime couldn't find FPGA hardware!
    if (e.code().value() == CL_DEVICE_NOT_FOUND) {
      std::cerr << "If you are targeting an FPGA, please ensure that your "
                   "system has a correctly configured FPGA board.\n";
      std::cerr << "Run sys_check in the oneAPI root directory to verify.\n";
      std::cerr << "If you are targeting the FPGA emulator, compile with "
                   "-DFPGA_EMULATOR.\n";
    }
    std::terminate();
  }

  // At this point, the device buffers have gone out of scope and the kernel
  // has been synchronized. Therefore, the output data (vec_r) has been updated
  // with the results of the kernel and is safely accesible by the host CPU.

  // Test the results
  size_t correct = 0;
  for (size_t i = 0; i < kArraySize*kArraySize; i++) {
    float tmp = vec_a[i] + vec_b[i] - vec_r[i];
    if (tmp * tmp < kTol * kTol) {
      correct++;
    }
  }

  // Summarize results
  if (correct == kArraySize*kArraySize) {
    std::cout << "PASSED: results are correct\n";
  } else {
    std::cout << "FAILED: results are incorrect\n";
  }

  return !(correct == kArraySize);
}

kernel.hpp code

//==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/sycl.hpp>

using namespace sycl;

void RunKernel(queue& q, buffer<float,2>& buf_a, buffer<float,2>& buf_b,
               buffer<float,2>& buf_r, size_t size,size_t wgs);

kernel.cpp code

//==============================================================
// Copyright Intel Corporation
//
// SPDX-License-Identifier: MIT
// =============================================================
#include <sycl/ext/intel/fpga_extensions.hpp>

#include "kernel.hpp"


// This file contains 'almost' exclusively device code. The single-source SYCL
// code has been refactored between host.cpp and kernel.cpp to separate host and
// device code to the extent that the language permits.
//
// Note that ANY change in either this file or in kernel.hpp will be detected
// by the build system as a difference in the dependencies of device.o,
// triggering a full recompilation of the device code. 
//
// This is true even of trivial changes, e.g. tweaking the function definition 
// or the names of variables like 'q' or 'h', EVEN THOUGH these are not truly 
// "device code".


// Forward declare the kernel names in the global scope. This FPGA best practice
// reduces compiler name mangling in the optimization reports.
class VectorAdd;

void RunKernel(queue& q, buffer<float,2>& buf_a, buffer<float,2>& buf_b,
               buffer<float,2>& buf_r, size_t size, size_t wgs){
    // submit the kernel
    q.submit([&](handler &h) {
      // Data accessors
      accessor a(buf_a, h, read_only);
      accessor b(buf_b, h, read_only);
      accessor r(buf_r, h, write_only, no_init);

      // Kernel executes with pipeline parallelism on the FPGA.
      // Use kernel_args_restrict to specify that a, b, and r do not alias.
      h.parallel_for<VectorAdd>(nd_range(range(size,size),range(wgs,wgs)),[=](nd_item<2> item) [[intel::kernel_args_restrict, sycl::reqd_work_group_size(16,16)]] {
        size_t i = item.get_global_id(0);
        size_t j = item.get_global_id(1);
        r[{i,j}] = a[{i,j}] + b[{i,j}];
      });
    });
}

compilation messages

/usr/bin/cmake -S/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile -B/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2 --check-build-system CMakeFiles/Makefile.cmake 0
make -f CMakeFiles/Makefile2 fpga
make[1]: Entering directory '/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2'
/usr/bin/cmake -S/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile -B/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2 --check-build-system CMakeFiles/Makefile.cmake 0
/usr/bin/cmake -E cmake_progress_start /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2/CMakeFiles 6
make -f CMakeFiles/Makefile2 CMakeFiles/fpga.dir/all
make[2]: Entering directory '/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2'
make -f CMakeFiles/displayHostCompileCommand.dir/build.make CMakeFiles/displayHostCompileCommand.dir/depend
make[3]: Entering directory '/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2'
cd /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2 && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2 /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2 /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2/CMakeFiles/displayHostCompileCommand.dir/DependInfo.cmake --color=
Scanning dependencies of target displayHostCompileCommand
make[3]: Leaving directory '/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2'
make -f CMakeFiles/displayHostCompileCommand.dir/build.make CMakeFiles/displayHostCompileCommand.dir/build
make[3]: Entering directory '/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2'
[ 16%] To run the host code compile manually:
 /opt/intel/oneapi/compiler/2024.1/bin/icpx -fintelfpga -Wall -qactypes -DFPGA_HARDWARE -c /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/src/host.cpp -o host.o -I/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/../../../include
/usr/bin/cmake -E cmake_echo_color --cyan 
make[3]: Leaving directory '/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2'
[ 16%] Built target displayHostCompileCommand
make -f CMakeFiles/displayFPGALinkCompileCommand.dir/build.make CMakeFiles/displayFPGALinkCompileCommand.dir/depend
make[3]: Entering directory '/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2'
cd /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2 && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2 /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2 /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2/CMakeFiles/displayFPGALinkCompileCommand.dir/DependInfo.cmake --color=
Scanning dependencies of target displayFPGALinkCompileCommand
make[3]: Leaving directory '/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2'
make -f CMakeFiles/displayFPGALinkCompileCommand.dir/build.make CMakeFiles/displayFPGALinkCompileCommand.dir/build
make[3]: Entering directory '/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2'
[ 33%] To run the FPGA link compile manually:
 /opt/intel/oneapi/compiler/2024.1/bin/icpx -fintelfpga -qactypes host.o kernel_image.a -o fast_recompile.fpga -I/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/../../../include
/usr/bin/cmake -E cmake_echo_color --cyan 
make[3]: Leaving directory '/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2'
[ 33%] Built target displayFPGALinkCompileCommand
make -f CMakeFiles/displayDeviceCompileCommand.dir/build.make CMakeFiles/displayDeviceCompileCommand.dir/depend
make[3]: Entering directory '/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2'
cd /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2 && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2 /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2 /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2/CMakeFiles/displayDeviceCompileCommand.dir/DependInfo.cmake --color=
Scanning dependencies of target displayDeviceCompileCommand
make[3]: Leaving directory '/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2'
make -f CMakeFiles/displayDeviceCompileCommand.dir/build.make CMakeFiles/displayDeviceCompileCommand.dir/build
make[3]: Entering directory '/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2'
[ 50%] To run the device code compile manually:
 /opt/intel/oneapi/compiler/2024.1/bin/icpx -fintelfpga -Wall -qactypes -DFPGA_HARDWARE -fintelfpga -qactypes -Xshardware -Xstarget=de10_agilex:B2E2_8GBx4 -Xsclock=50MHz -Xsseed=2 -reuse-exe=/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2/fast_recompile.fpga -fsycl-link=image /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/src/kernel.cpp -o kernel_image.a -I/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/../../../include
/usr/bin/cmake -E cmake_echo_color --cyan 
make[3]: Leaving directory '/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2'
[ 50%] Built target displayDeviceCompileCommand
make -f CMakeFiles/fpga.dir/build.make CMakeFiles/fpga.dir/depend
make[3]: Entering directory '/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2'
cd /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2 && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2 /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2 /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2/CMakeFiles/fpga.dir/DependInfo.cmake --color=
Scanning dependencies of target fpga
make[3]: Leaving directory '/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2'
make -f CMakeFiles/fpga.dir/build.make CMakeFiles/fpga.dir/build
make[3]: Entering directory '/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2'
[ 66%] Generating host.o
/opt/intel/oneapi/compiler/2024.1/bin/icpx -fintelfpga -Wall -qactypes -DFPGA_HARDWARE -c /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/src/host.cpp -o host.o -I/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/../../../include
[ 83%] Generating kernel_image.a
/opt/intel/oneapi/compiler/2024.1/bin/icpx -fintelfpga -Wall -qactypes -DFPGA_HARDWARE -fintelfpga -qactypes -Xshardware -Xstarget=de10_agilex:B2E2_8GBx4 -Xsclock=50MHz\ -Xsseed=2 -reuse-exe=/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2/fast_recompile.fpga -fsycl-link=image /home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/src/kernel.cpp -o kernel_image.a -I/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/../../../include
warning: -reuse-exe file '/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2/fast_recompile.fpga' not found; ignored
aoc: Compiling for FPGA. This process may take several hours to complete.  Prior to performing this compile, be sure to check the reports to ensure the design will meet your performance targets.  If the reports indicate performance targets are not being met, code edits may be required.  Please refer to the oneAPI FPGA Optimization Guide for information on performance tuning applications for FPGAs.
[100%] Generating fast_recompile.fpga
/opt/intel/oneapi/compiler/2024.1/bin/icpx -fintelfpga -qactypes host.o kernel_image.a -o fast_recompile.fpga -I/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/../../../include
libc++abi: terminating due to uncaught exception of type std::bad_alloc: std::bad_alloc
 #0 0x000056039960bd73 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/opt/intel/oneapi/compiler/2024.1/bin/compiler/clang-offload-wrapper+0x3afd73)
 #1 0x000056039960a232 llvm::sys::RunSignalHandlers() (/opt/intel/oneapi/compiler/2024.1/bin/compiler/clang-offload-wrapper+0x3ae232)
 #2 0x000056039960c504 SignalHandler(int) Signals.cpp:0:0
 #3 0x00007fc149201420 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x14420)
 #4 0x00007fc14903e00b raise /build/glibc-LcI20x/glibc-2.31/signal/../sysdeps/unix/sysv/linux/raise.c:51:1
 #5 0x00007fc14901d859 abort /build/glibc-LcI20x/glibc-2.31/stdlib/abort.c:81:7
 #6 0x0000560399715896 (/opt/intel/oneapi/compiler/2024.1/bin/compiler/clang-offload-wrapper+0x4b9896)
 #7 0x00005603996fe5db demangling_terminate_handler() cxa_default_handlers.cpp:0:0
 #8 0x0000560399715553 std::__terminate(void (*)()) cxa_handlers.cpp:0:0
 #9 0x0000560399716f36 (/opt/intel/oneapi/compiler/2024.1/bin/compiler/clang-offload-wrapper+0x4baf36)
#10 0x0000560399716ecf (/opt/intel/oneapi/compiler/2024.1/bin/compiler/clang-offload-wrapper+0x4baecf)
#11 0x0000560399716c28 operator new(unsigned long) (/opt/intel/oneapi/compiler/2024.1/bin/compiler/clang-offload-wrapper+0x4bac28)
#12 0x00005603995e6ca8 llvm::util::PropertyValue::PropertyValue(unsigned char const*, unsigned long) (/opt/intel/oneapi/compiler/2024.1/bin/compiler/clang-offload-wrapper+0x38aca8)
#13 0x00005603994758dd SymPropReader::getPropRegistry() (/opt/intel/oneapi/compiler/2024.1/bin/compiler/clang-offload-wrapper+0x2198dd)
#14 0x000056039946cc22 (anonymous namespace)::BinaryWrapper::createBinDesc(OffloadKind, llvm::SmallVector<std::__1::unique_ptr<(anonymous namespace)::BinaryWrapper::Image, std::__1::default_delete<(anonymous namespace)::BinaryWrapper::Image>>, 4u>&) ClangOffloadWrapper.cpp:0:0
#15 0x00005603994654de main (/opt/intel/oneapi/compiler/2024.1/bin/compiler/clang-offload-wrapper+0x2094de)
#16 0x00007fc14901f083 __libc_start_main /build/glibc-LcI20x/glibc-2.31/csu/../csu/libc-start.c:342:3
#17 0x0000560399461529 _start (/opt/intel/oneapi/compiler/2024.1/bin/compiler/clang-offload-wrapper+0x205529)
icpx: error: unable to execute command: Aborted (core dumped)
icpx: error: clang-offload-wrapper command failed due to signal (use -v to see invocation)
Intel(R) oneAPI DPC++/C++ Compiler 2024.1.0 (2024.1.0.20240308)
Target: x86_64-unknown-linux-gnu
Thread model: posix
InstalledDir: /opt/intel/oneapi/compiler/2024.1/bin/compiler
Configuration file: /opt/intel/oneapi/compiler/2024.1/bin/compiler/../icpx.cfg
icpx: note: diagnostic msg: Error generating preprocessed source(s).
make[3]: *** [CMakeFiles/fpga.dir/build.make:65: fast_recompile.fpga] Error 1
make[3]: Leaving directory '/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2'
make[2]: *** [CMakeFiles/Makefile2:144: CMakeFiles/fpga.dir/all] Error 2
make[2]: Leaving directory '/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2'
make[1]: *** [CMakeFiles/Makefile2:151: CMakeFiles/fpga.dir/rule] Error 2
make[1]: Leaving directory '/home/diegog/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/GettingStarted/fast_recompile/build_reqd_2'
make: *** [Makefile:147: fpga] Error 2