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RubenPadial's avatar
RubenPadial
Icon for Contributor rankContributor
2 years ago

Error (23035) Tcl error running dla_build_example_design.py script

Hello, I got this error when I run "dla_build_example_design.py" esample script with Intel FPGA AI suite. It is run according to the "Intel FPGA AI Suite SoC Design Example User Guide" and it s...
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JohnT_Altera's avatar
JohnT_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


Have you try compiling with Nios V design? Appreciate your feedback


  • RubenPadial's avatar
    RubenPadial
    Icon for Contributor rankContributor
    2 years ago

    Hello @JohnT_Intel,

    sorry for the late answer.

    I'm not familiar with Nios V design so I followed the Nios® V Processor Example Design aand downloaded the top.par file. I attempted to compile Nios V from scratch using the build_sof.py script according to readme.txt file. Unfortubnately, I got a license error:
    FlexNet Licensing error:-140,148.
    Error (13223): Verilog HDL or VHDL error: cannot open Verilog file 'ip/sys/cpu/intel_niosv_m_unit_2141/synth/opcode_def.sv'