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tde_m's avatar
tde_m
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

DSP Double Pumping

Following an old question (https://forums.intel.com/s/question/0D50P00004MInzpSAD/double-pumping-dsp-units-ip) is there any way to allow double pumping of DSPs in Stratix 10 and to exploit this direc...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

Double pumping does work on S10. You can apply the attribute doublepump to request double pumping for a given array. Will request to have it on dsp for the future. Thanks

  • tde_m's avatar
    tde_m
    Icon for Occasional Contributor rankOccasional Contributor
    6 years ago

    Thanks!

    In your opinion, would it be possible to implement it as RTL block? Does OpenCL compiler/designs provide everything that I would need for that?

    I could not find any useful documentation for this.

    Thanks

  • HRZ's avatar
    HRZ
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    @KennyT_Intel​ This is not true, Section 10.3 of the documentation (https://www.intel.com/content/www/us/en/programmable/documentation/mwh1391807516407.html#jhl1520273455239) clearly states that no 2x clock is provided in the design by the compiler for Stratix 10 and hence, Block RAM double-pumping is not available on Stratix 10. This also means that any type of double-pumping cannot be implemented by the user in RTL either since there is no 2x clock in the system generated by the compiler.

    • KennyT_altera's avatar
      KennyT_altera
      Icon for Super Contributor rankSuper Contributor
      6 years ago

      Thanks for pointing out, the attribute doublepump for Startix 10 should be working. The compiler may not infer double-pumping my default, but the attribute should always be able to override that.

      Will have this documentation corrected.

    • HRZ's avatar
      HRZ
      Icon for Frequent Contributor rankFrequent Contributor
      6 years ago

      Interesting; I just tested Block RAM double-pumping on Stratix 10 and indeed it seems to work. All this time I was thinking it won't work because the documentation said so. Having DSP double-pumping on top of that will be extremely valuable and a huge advantage over the main competitor's HLS compiler (among numerous other advantages that Intel's HLS compiler has). In fact, on Stratix 10 there is probably room to even do triple-pumping, considering how high the peak operating frequency of the Block RAMs and the DSPs is compared to typical kernel frequency.