Forum Discussion
tde_m
Occasional Contributor
6 years agoDSP Double Pumping
Following an old question (https://forums.intel.com/s/question/0D50P00004MInzpSAD/double-pumping-dsp-units-ip) is there any way to allow double pumping of DSPs in Stratix 10 and to exploit this direc...
HRZ
Frequent Contributor
6 years agoThe OpenCL compiler does not support DSP double-pumping and in fact, even Block RAM double-pumping that was supported for older FPGAs (Stratix V and Arria 10) has been disabled for Stratix 10. Even though this would be a very useful feature since kernels on Stratix 10 tend to run at far lower frequencies than the promised 800-900 MHz, seeing how even the existing Block RAM double-pumping was disabled for Stratix 10, I would not expect DSP double-pumping to ever be supported. The option to implement DSP double-pumping manually in RTL and using it as an RTL blackbox in OpenCL theoretically exists, but it won't be easy to implement and I am not sure if the OpenCL compiler provides a 2x clock on Stratix 10 anymore (or at all).