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TMerz
New Contributor
New ContributorDSP builder compilation error
Hello community, I'm using the DSP builder to design the behaviour of my logic which shall be converted to VHDL to use it on my Cyclone IV FPGA board. I want to use some LUTs and I have a strange b...
JeffC_Altera
Occasional Contributor
Occasional ContributorIf this is a standalone LUT (assuming part of a bigger design) - try bookending the LUT with GPIn and GPOut blocks and drop a SynthesisInfo block. In this case, latency=0 - true lookup table / not registered - and it did build fine in Q18.1 w/ R2019a.
In this case, lut_values is designated as the contents in the LUT block.
From setup .m file:
lut_values = zeros(1,16);
Jeff
