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Ghe0rghe's avatar
Ghe0rghe
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Downsample block and TDM/TDD blocks in DSPBuilder Advanced Blockset

Hello all, I am porting a project over from Xilinx System Generator to DSPBuilder advanced blockset. Xilinx system generator includes three handy blocks that do not seem to be present in DSP Builde...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    5 years ago

    Hi,


    You may need a dual clock FIFO to transfer data between two different clock domains.


    Regards -SK


SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


You may need a dual clock FIFO to transfer data between two different clock domains.


Regards -SK


  • Ghe0rghe's avatar
    Ghe0rghe
    Icon for New Contributor rankNew Contributor
    5 years ago

    Ok thank you.

    Using a secondary clock, and associating it to output signals going to a custom component with lower clock rate seems to work.