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Ghe0rghe
New Contributor
New ContributorDownsample block and TDM/TDD blocks in DSPBuilder Advanced Blockset
Hello all,
I am porting a project over from Xilinx System Generator to DSPBuilder advanced blockset. Xilinx system generator includes three handy blocks that do not seem to be present in DSP Builde...
Hi,
You may need a dual clock FIFO to transfer data between two different clock domains.
Regards -SK
SengKok_L_Intel
Regular Contributor
Regular ContributorHi,
You may need a dual clock FIFO to transfer data between two different clock domains.
Regards -SK
Ghe0rgheOk thank you.
Using a secondary clock, and associating it to output signals going to a custom component with lower clock rate seems to work.
