Forum Discussion

Ghe0rghe's avatar
Ghe0rghe
Icon for New Contributor rankNew Contributor
6 years ago
Solved

Downsample block and TDM/TDD blocks in DSPBuilder Advanced Blockset

Hello all, I am porting a project over from Xilinx System Generator to DSPBuilder advanced blockset. Xilinx system generator includes three handy blocks that do not seem to be present in DSP Builde...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    5 years ago

    Hi,


    You may need a dual clock FIFO to transfer data between two different clock domains.


    Regards -SK


SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Multirate means the sample rate variation at different stages of a datapath, but it uses a single path clock domain.

The ModelIP block like CIC, decimation FIR or Interpolating FIR are running at different data rates between the input and output port, however, the clock domain is still the same.


Regards -SK


  • Ghe0rghe's avatar
    Ghe0rghe
    Icon for New Contributor rankNew Contributor
    5 years ago

    Ok, I see, thank you for the clarification.

    Is there a way to change a signal's data rate without using these multirate filters?

    How can I use the DSPBA blockset to downsample a signal's data rate by only sparsely sampling it at the lower data rate? I would like to avoid perturbing my signals' frequency content by avoiding these filters.

    Best,

    -Gheorghe