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Ghe0rghe's avatar
Ghe0rghe
Icon for New Contributor rankNew Contributor
5 years ago
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Downsample block and TDM/TDD blocks in DSPBuilder Advanced Blockset

Hello all, I am porting a project over from Xilinx System Generator to DSPBuilder advanced blockset. Xilinx system generator includes three handy blocks that do not seem to be present in DSP Builde...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    5 years ago

    Hi,


    You may need a dual clock FIFO to transfer data between two different clock domains.


    Regards -SK


SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

The DSP builder system is support single clock domain, and there is NO down or up sampling block as I can see. For the TDM block, you may consider to use the DEMUX in primitive library, it has the same function as ChanView.

Regards -SK


Ghe0rghe's avatar
Ghe0rghe
Icon for New Contributor rankNew Contributor
5 years ago

Are you sure that Intel DSP Builder subsystems only support single clock domain?

This video seems to suggest otherwise.

https://youtu.be/stKdxz802GA?t=1249

At the 20:50 mark, the video references another training video called "Building MultiRate DSP Builder Design Training", but I cannot seem to find this other "Multirate" video/training document anywhere?

If you know more about this, please let me know, thank you.

- Gheorghe S