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Ghe0rghe's avatar
Ghe0rghe
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6 years ago
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Downsample block and TDM/TDD blocks in DSPBuilder Advanced Blockset

Hello all, I am porting a project over from Xilinx System Generator to DSPBuilder advanced blockset. Xilinx system generator includes three handy blocks that do not seem to be present in DSP Builde...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    5 years ago

    Hi,


    You may need a dual clock FIFO to transfer data between two different clock domains.


    Regards -SK


Ghe0rghe's avatar
Ghe0rghe
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6 years ago

Thank you SengKok

About the downsampling block: Does this imply that Intel DSP Builder subsystems cannot be "multirate"? I would like to integrate the downsampling block in my DSPBuilder-generated RTL. Maybe can you refer me to a triggered sample-and-hold block in the DSPBA Blockset to accomplish this?

Thank you,

- Gheorghe

Ghe0rghe's avatar
Ghe0rghe
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6 years ago

Also, about the TDM block:

Perhaps I can use the ChanView block in the DSPBA blockset? Do you see any problems with using this block? I suspect that this block won't work because it is reserved for RTL simulations in MATLAB, and does not actually get implemented in DSPBuilder-generated RTL.

Best,

- Gheorghe