New Contributor
Hi,
You may need a dual clock FIFO to transfer data between two different clock domains.
Regards -SK
Regular ContributorHi,
The design flow for DSP Builder may be slightly different from others. The downsampling block is not available from the DSP builder library, however, for simulation purposes, you can use the downsample block from DSP System Toolbox. You can see the example design “demo_firs” example at this directory “installation path\quartus\dspba\Examples\Filters” is using it for simulation purposes (not part of the RTL).
For the TDM, probably you can refer to the DEMUX/MUX block from the primitive library.
Regards -SK
New ContributorThank you SengKok
About the downsampling block: Does this imply that Intel DSP Builder subsystems cannot be "multirate"? I would like to integrate the downsampling block in my DSPBuilder-generated RTL. Maybe can you refer me to a triggered sample-and-hold block in the DSPBA Blockset to accomplish this?
Thank you,
- Gheorghe
New ContributorAlso, about the TDM block:
Perhaps I can use the ChanView block in the DSPBA blockset? Do you see any problems with using this block? I suspect that this block won't work because it is reserved for RTL simulations in MATLAB, and does not actually get implemented in DSPBuilder-generated RTL.
Best,
- Gheorghe
