DL models on FPGA with OpenVINO

Hi,

thanks so much for the replies! Now it's much clearer!

1) So, for example, if a particular layer is supported by the FPGA plug-in, in reality this may not be executed on the FPGA if it is not foreseen by the bitstream loaded on the board. Did I get it right?

2) Also I saw that you can specify "-l <CPU_EXTENSION>" to expand the levels supported by the CPU plug-in. Is there something similar for FPGA? Or not?

This is a general discussion, not necessarily regarding terasic kits.

Thanks in advance

Best regards.

Vincenzo