Forum Discussion
New ContributorDeveloping a high speed stopwatch
Frequent ContributorOk, I don't understand why you did not start here ....
https://github.com/vidor-libraries/VidorFPGA
It is a template project, with the top level verilog module defined, as well as supporting .qpf, .qsf, and .sdc files for a fully constrained compilation.
It appears that the iCLK coming into the FPGA is 8MHz, and the internal PLL is used to generate 24MHz and 120MHz clocks for on chip use.
FvMSuper Contributor
Don't want to argue why your internal clock generation method isn't reliable. Just take as granted that it's beyond any FPGA specification and not supported by Quartus. And not necessary because you can easily generate a wide range of legal clock frequencies with built-in PLL.
Quartus timing analyzer tells that fmax of basic 64 bit synchronous binary counter used in your design is about 150 MHz for Cyclone 10 speed class 8 and 200 MHz for fastest speed class 6.
Another basic problem of your design is iLatch1,2 being asynchronous to iCLK. Respectively it's not guaranteed to latch counter value consistently. In a regular design, iLatch has to be synchronized to iCLK or counter value gray encoded.
